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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:32:59 11/23/2017 
-- Design Name: 
-- Module Name:    bscontrol - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity bscontrol is
Port ( key : in STD_LOGIC;
enable : out STD_LOGIC);
end bscontrol;

architecture Behavioral of bscontrol is
signal en: std_logic:='0';
begin


process(key)
begin
if key'event and key='1' then
en<= not en;
end if;
enable<= en;
end process;
end Behavioral;
